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19-2936; Rev 0; 7/03
10.7Gbps Adaptive Receive Equalizer
General Description
The MAX3805 is designed to provide up to 30in (0.75m) reach on 6-mil differential FR-4 transmission line, or up to 24ft (8m) on RG-188A/U type coaxial cable, for PRBS data from 9.95Gbps to 10.7Gbps. The MAX3805 adaptive equalizer reduces intersymbol interference, resulting in 20ps residual jitter after equalization. An internal feedback network controls the equalizer to automatically match frequency-dependent skin effect and dielectric losses. The MAX3805 provides LVCMOS-compatible output-enable and signaldetect functions. The MAX3805 has separate supply connections for the internal logic and I/O circuits. This allows the currentmode logic (CML) input and CML output to be connected to isolated supplies for independent DC-coupled interfaces to 1.8V, 2.5V, or 3.3V ICs. The MAX3805 comes in a very small 3mm x 3mm package and consumes only 135mW. o 3mm x 3mm Package o Spans 30in (0.75m) of 6-mil FR-4 o Spans 24ft (8m) of Coax o Automatic Receive Equalization to Reduce ISI Caused by Path Losses o Up to 10.7Gbps NRZ Data Operating Range o Signal-Detect Output o Output-Enable Control o 135mW Power Consumption o DC-Coupled Input and Output to Terminations as Low as 1.65V o Differential or Single-Ended Operation o +3.3V Core Power Supply
Features
MAX3805
Applications
OC-192, 10GbE Switches and Routers OC-192, 10GbE Serial Modules High-Speed Signal Distribution
PART MAX3805ETE
Ordering Information
TEMP RANGE PINPACKAGE PACKAGE CODE T1633F-3
-40C to +85C 16 Thin QFN
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
LINE CARD 2.5V SWITCH CARD 1.8V
+3.3V 10Gbps CDR/SERDES 10Gbps SWITCH
VCC1
VCC
VCC2
Tx
2 +3.3V
FR-4 STRIPLINE 2 PC BOARD BACKPLANE
SDI
MAX3805
SD EN
SDO 2 2
Rx
VCC 2 Rx 2 SDO VCC2
MAX3805
2 SDI FR-4 STRIPLINE
2 Tx
SD EN VCC1
2.5V
1.8V
________________________________________________________________ Maxim Integrated Products
1
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10.7Gbps Adaptive Receive Equalizer MAX3805
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ............................................-0.5V to +4.0V CML Supply Voltage (VCC1, VCC2) ..........................................-0.5V to (VCC + 0.5V) Current at SDO...............................................................25mA SDI, EN, SD, HFPD, LFPD........................-0.5V to (VCC + 0.5V) Current at HFPD, LFPD ......................................................400A Continuous Power Dissipation (TA = +85C) 16-Lead QFN-EP (derate 17.5mW/C above +85C) ............................................................1398mW Operating Ambient Temperature Range .............-40C to +85C Storage Ambient Temperature Range...............-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER Supply Voltage Input Termination Voltage Output Termination Voltage Operating Ambient Temperature SYMBOL VCC VCC1 VCC2 CONDITIONS MIN 3.0 1.65 1.65 -40 +25 TYP 3.3 MAX 3.6 VCC VCC +85 UNITS V V V C
ELECTRICAL CHARACTERISTICS
(Pin 13 (HFPD) and pin 14 (LFPD) are not connected. Typical values are at VCC = +3.3V, VCC1 = VCC2 = 1.8V, TA = +25C, unless otherwise noted.) (Values at -40C are guaranteed by design and characterization.)
PARAMETER Supply Current CML Input Differential Voltage CML Input Common-Mode Voltage CML Input Resistance CML Input Return Loss CML Output Differential Voltage CML Output Resistance CML Output Transition Time CML Output Return Loss Equalizer Time Constant Output Residual Jitter Signal-Detect Assert Signal-Detect Deassert LVCMOS Input-High Leakage Current IH (Notes 3-6) PRBS231 - 1 at 10.7Gbps (Note 1) PRBS231 - 1 at 10.7Gbps (Note 1) +10 tr/tf VOUT Differential 100MHz to 10GHz VCC2 = 1.65V to 3.6V Differential 20% to 80% (Notes 2, 6) 100MHz to 5GHz 10 10 21 200 220 +60 30 400 85 SYMBOL ICC VIN CONDITIONS VCC = VCC1 = VCC2 AC-coupled or DC-coupled at transmission line input (Notes 1, 6) 400 1.3 85 100 10 500 100 600 115 35 MIN TYP 41 MAX 60 1200 VCC1 115 UNITS mA mVP-P V dB mVP-P ps dB s psP-P mVP-P mVP-P A
2
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10.7Gbps Adaptive Receive Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(Pin 13 (HFPD) and pin 14 (LFPD) are not connected. Typical values are at VCC = +3.3V, VCC1 = VCC2 = 1.8V, TA = +25C, unless otherwise noted.) (Values at -40C are guaranteed by design and characterization.)
PARAMETER LVCMOS Input-Low Leakage Current LVCMOS Input High LVCMOS Input Low LVCMOS Output High LVCMOS Output Low SYMBOL IL VIH VIL VOH VOL IOH = 12.5A IOL = 0.5mA 2.1 0.2 CONDITIONS MIN -30 1.5 0.5 TYP MAX +30 UNITS A V V V V
MAX3805
Note 1: Differential input sensitivity is defined at the input to a transmission line with path length up to 30in. Note 2: Measured using 10 ones and 10 zeros at 10.7Gbps. Note 3: Residual jitter is the difference in total jitter between the signal at the input to the transmission line and the equalizer output. Total residual jitter is DJP-P + 14.1 x RJRMS. Note 4: Measured at 10.7Gbps using a pattern of 100 ones, PRBS 210 - 1, 100 zeros, PRBS 210 - 1. Note 5: VIN = 400mVP-P to 1200mVP-P, input path is 0 to 30in, 6-mil microstrip in FR-4, r = 4.5, and tan = 0.02. Note 6: Guaranteed by design and characterization.
Typical Operating Characteristics
(VCC = 3.3V, VCC1 = 1.8V, VCC2 = 1.8V, and TA = +25C, unless otherwise noted.)
EQUALIZER INPUT EYE AFTER 30in OF FR-4 (210 - 1PRBS WITH 100 CIDs AT 9.953Gbps)
MAX3805 toc01
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (210 - 1PRBS WITH 100 CIDs AT 9.953Gbps)
MAX3805 toc02
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (231 - 1PRBS AT 10.7Gbps)
MAX3805 toc03
65mV/div
65mV/div
65mV/div
20ps/div
20ps/div
20ps/div
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10.7Gbps Adaptive Receive Equalizer MAX3805
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCC1 = 1.8V, VCC2 = 1.8V, and TA = +25C, unless otherwise noted.)
EQUALIZER OUTPUT EYE AFTER 24ft OF RG-188/U COAXIAL CABLE, SINGLE ENDED (223 - 1PRBS AT 10.7Gbps)
MAX3805 toc05
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (CJTPAT 10.0Gbps LFPD/(HFPD + LFPD) = 0.6)
MAX3805 toc04
SUPPLY CURRENT vs. TEMPERATURE
VCC = VCC1 = VCC2 = +3.3V 60 SUPPLY CURRENT (mA) 55 50 45 40 35
MAX3805 toc06
65
65mV/div
65mV/div
20ps/div
20ps/div
-40
-20
0
20
40
60
80
TEMPERATURE (C)
RESIDUAL JITTER vs. AMPLITUDE
MAX3805 toc07
RESIDUAL JITTER vs. FR-4 PATH LENGTH
DATA RATE = 10.7Gbps PATTERN = PRBS 210 -1 VIN = 400mVP-P
MAX3805 toc08
50 45 RESIDUAL JITTER (ps) 40 35
50 45 RESIDUAL JITTER 40 35 30 25 20
DATA RATE = 9.953Gbps PATTERN = PRBS 210 -1
RESIDUAL JITTER = DJ + 14.1 x RJ 30 25 20 FR4 = 18in 15 400 500 600 700 800 900 1000 1100 1200 AMPLITUDE (mVP-P) FR4 = 30in
RESIDUAL JITTER = DJ + 14.1 x RJ 15 3 6 9 12 15 18 21 24 27 30 FR-4 PATH LENGTH (in)
RESIDUAL JITTER vs. DATA RATE
MAX3805 toc09
RESIDUAL JITTER vs. RLFPD/(RHFPD + RLFPD)
VIN = 400mVP-P PATTERN = CJTPAT DATA RATE = 10.0Gbps (RLFPD + RHFPD) = 100k
MAX3805 toc10
50 45 RESIDUAL JITTER (ps) 40 35 30 25 20 15
50 45 RESIDUAL JITTER (ps) 40 35 30 25 20
VIN = 400mVP-P PATTERN = 100 1's PRBS 210-1 100 0's PRBS 210-1 RESIDUAL JITTER = DJ + 14.1 x RJ
18in FR4
30in FR4
18in FR4 10 6 7 8 9 10 11 DATA RATE (Gbps) 15
RESIDUAL JITTER = DJ + 14.1 x RJ 0.5 0.6 0.7
30in FR4 0.8 0.9
RLFPD/(RHFPD + RLFPD)
4
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10.7Gbps Adaptive Receive Equalizer
Pin Description
PIN 1 2 3 4 5 6 7 8 9, 12 10 11 13 14 15 16 EP NAME VCC1 SDI+ SDIVCC1 GND SD EN GND VCC2 SDOSDO+ HFPD LFPD VCC GND Exposed Pad Supply Voltage, CML Input (1.8V to VCC) Positive Differential Serial Data Input, CML Negative Differential Serial Data Input, CML Supply Voltage, CML Input (1.8V to VCC) Supply Ground Signal-Detect Output, LVCMOS. Low indicates <200mVP-P, high indicates >220mVP-P. Enable Input, LVCMOS. Low disables output, high enables output, typically connected to SD. Supply Ground Supply Voltage, CML Output (1.8V to VCC) Negative Differential Serial Data Output, CML Positive Differential Serial Data Output, CML High-Frequency Power Detector. Leave open for 9.953Gbps to 10.7Gbps PRBS NRZ data. Low-Frequency Power Detector. Leave open for 9.953Gbps to 10.7Gbps PRBS NRZ data. Supply Voltage, Equalizer Core, 3.3V Supply Ground Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. FUNCTION
MAX3805
Detailed Description and Applications Information
The MAX3805 adaptive equalizer is designed to operate with 9.95Gbps to 10.7Gbps PRBS nonreturn-to-zero (NRZ) data at the receive end of a transmission line, typically differential 6-mil FR-4 PC board. It adaptively corrects intersymbol interference caused by frequencydependent path loss. It can also be used with coaxial cable links and with transmission lines that include wellengineered connectors, as long as the total path loss is relatively smooth and does not exceed 20dB at 5GHz. The signal path for the MAX3805 consists of a CML input stage, two amplifiers feeding a pair of variable attenuators controlled by feedback, and a limiting amplifier with a CML output stage. An enable input, EN, is used to control the output stage. A signal-detect output, SD, indicates when input signal to the transmission line is above 220mVP-P or below 200mVP-P, typically. See the Functional Diagram.
CML Input and Output Buffers
The MAX3805 CML input and output buffers are internally terminated with 50 to VCC1 and VCC2, respectively. The input and output circuitry have separate voltage connections to control noise coupling and provide DC-coupling to +1.8V, +2.5V, or +3.3V CML. If desired, the CML inputs and outputs can be AC-coupled. See Figure 1 for the output structure. The low-frequency cutoff of the input-stage offset-cancellation circuit is nominally 21kHz. For single-ended operation (typically coaxial cable links), the input must be AC-coupled; connect the unused input to VCC1 using a series combination of an AC-coupling capacitor and a 50 resistor, as shown in Figure 2. Note that the MAX3805 is specified for differential operation, and the performance may be reduced in single-ended operation.
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5
10.7Gbps Adaptive Receive Equalizer MAX3805
Functional Diagram
VCC1 VCC VCC2
FLAT AMP
VARIABLE ATTENUATOR
SDI+ CML IN SDIBOOST AMP VARIABLE ATTENUATOR
SDO+
LIMITING AMP
CML OUT SDOEN
LF POWER DETECTOR
MAX3805
LOOP FILTER SIGNAL DETECT
POWER DETECTOR
LFPD
HFPD
SD
Input Stage with Equalization
The low-noise input stage of the MAX3805 includes two amplifiers, one with flat frequency response and the other with a highpass frequency response compensating for the loss characteristic of 6-mil FR-4 PC board transmission line. A current-steering network, implemented with a pair of variable attenuators feeding into a common summing node, provides the means to continuously vary the amount of equalization. The amount of equalization is controlled by feedback from two powerdetector blocks that set the variable attenuators to match the loss of a particular transmission path.
VCC2 VCC
50
50 OUT+ OUT-
ESD STRUCTURES
Dual Power-Detector Feedback Loop
The MAX3805 adapts the equalizer to a specific path loss by sampling the output of the summing node with a pair of frequency-dependent power detectors. The first power detector has a lowpass bandwidth of 500MHz; the second power detector has full bandwidth. NRZ PRBS data has a sin2(f)/f2 spectral characteristic. When this data is passed through a lossy FR-4 path, high-frequency components are attenuated, while low-
Figure 1. CML Output Structure
6
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10.7Gbps Adaptive Receive Equalizer MAX3805
VCC 50 TRANSMISSION LINE 0.01F IN+ VCC1 50 0.01F IN500k
MAX3805
LFPD HFPD
MAX3805 Figure 2. Single-Ended Operation Figure 3. Connecting a Potentionmeter Across HFPD and LFPD
frequency components remain essentially intact. These changes in the spectral characteristic of the signal at the output of the path are measured with the two power detectors to provide a means to determine the path loss. The dual power-detector feedback loop measures the ratio between the outputs of the two power detectors and adjusts the attenuation to restore the sin 2 (f)/f 2 characteristic. The time constant for this feedback loop is nominally 10s.
Signal Detect
The output of the high-frequency power detector is used to generate an LVCMOS-compatible signal-detect (SD) output. The SD output asserts when the input signal at the transmission line falls below 200mVP-P, and deasserts when the input signal at the transmission line rises above 220mVP-P. The SD output can be directly connected to the EN input to disable the MAX3805 output when no data signal is available. The SD output has an LVCMOS fanout of one.
Operating with Different Data Rates and Codes
The MAX3805 equalizer feedback loop is optimized for 9.95Gbps to 10.7Gbps NRZ PRBS data; however, it can also be used at a lower data rate or with a different coding type by adjusting the feedback loop. The relative gain of the two power detectors can be adjusted by connecting a 500k trimmer potentiometer between HFPD and LFPD pins, with the wiper connected to VCC, as shown in Figure 3. Set the trimmer potentiometer for the best eye opening. Adding the potentiometer between HFPD and LFPD can change the assert and deassert levels of the signal detector, which could render the signal-detect output invalid. For normal operation with 9.953Gbps to 10.7Gbps PRBS NRZ data, these signals should be left open with no connections to pin 13 (HFPD) or pin 14 (LFPD). Note that excessive capacitance on pin 13 or pin 14 can affect the operation of the feedback loop. Make certain that the PC board traces from these pins to the trimmer potentiometer are kept short.
Package and Layout Considerations
The MAX3805 is packaged in a 3mm x 3mm plasticencapsulated 16-lead thin QFN package with exposed pad for signal integrity. The exposed pad provides thermal and electrical connectivity to the IC, and must be soldered to a high-frequency ground plane. Use good layout techniques for the10Gbps SDI and SDO PC board transmission lines, and configure the trace geometry near the IC package to minimize impedance discontinuities. Power-supply decoupling capacitors should be provided for each supply connection and located as close as practical to the IC package.
VCC
60k SD
Enable Function
The EN output is an LVCMOS-compatible pin that enables the output stage of the MAX3805. Connect EN to VCC or LVCMOS high to enable the output stage of the device or to GND or LVCMOS low to disable the output stage of the device.
ESD STRUCTURES
Figure 4. Signal-Detect Output Circuit
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7
10.7Gbps Adaptive Receive Equalizer MAX3805
Chip Information
GND
Pin Configuration
HFPD
16 VCC1 SDI+ SDIVCC1 1 2 3 4 5 GND
15
14
LFPD
VCC
TRANSISTOR COUNT: 1647 PROCESS: SiGe Bipolar
13 12 VCC2 SDO+ SDOVCC2
MAX3805
11 10 9
6
SD
7 EN
8 GND
*EXPOSED PAD IS CONNECTED TO GND
8
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10.7Gbps Adaptive Receive Equalizer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
MAX3805
D2 b
0.10 M C A B
D D/2
D2/2
E/2
E2/2
C L
-A-
E
(NE - 1) X e
E2
L
-B-
e
k (ND - 1) X e
C L
C L
0.10 C 0.08 C
C L
A A2 A1 L L
e
e
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0136
1 2
C
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9
10.7Gbps Adaptive Receive Equalizer MAX3805
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0136
2 2
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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